Digital electronic devices utilize integrated circuits. Consumer expectations of high quality demands that extensive testing of the integrated circuits be performed prior to integration into an end device.
Integrated circuit manufacturers utilize large automated testers to perform entire suites of tests on integrated circuits prior to shipment. In general, a test to be performed on an integrated circuit device under test (hereinafter “DUT”) consists of a set of pattern vectors that translate to stimulus voltage levels to be applied to input signal pins of the DUT according to pre-specified timing. Signals captured from output signal pins of the DUT are translated into corresponding response vectors that may be analyzed to determine whether the DUT is operating according to specification.
Integrated circuits typically include a number of signal pins used for input and output of “interesting” signals. The signal pins are typically electrically connected to test points on a board. For example, an integrated circuit may be mounted on a printed circuit board. Alternatively, an integrated circuit may be packaged and mounted in a handler (e.g., a socket) for testing. Sockets also exist for integrated circuit dies that are not yet packaged, and even (in the form of a translator board) for the semiconductor wafer on which the integrated circuit is manufactured is not yet even diced. A tester traditionally provides a set of tester interface pins which are designed to electrically connect, typically through a test fixture, to the test points on the handler. As stated previously, the test points are electrically connected to signal pins of the DUT. The conductive paths between the test points up to and including the signal pins of the DUT are traditionally called the “DUT channels”.
The tester generally provides a number of signal generating resources that may generate configurable signal levels with configurable timing. The tester also provides signal processing resources capable of converting signals generated by a DUT (e.g., the analog form) into a format (e.g., the digital form) readable by the tester. The signal processing resources may also be configurable. The tester may be configured (by way of a set of relays) to electrically connect any tester resource to any tester interface pin. This process is referred to as “PE channel configuration”. The electrical path between a given tester resource up to and including the tester interface pin that the resource is configured to connect to is referred to as a “pin electronics channel” (or “PE channel”).
To test a DUT, the DUT is mounted on the tester such that the test points connected to DUT channels are probed by predetermined tester interface pins. The tester is configured to connect appropriate tester resources to each of the probed DUT channels by way of a PE channel. DUT channels electrically connect to PE channels in a one-to-one mapping. Various other configurations is required, for example specifying the DUT layout and setting up a given test, but ultimately the tester applies test vectors to, and receives test responses from, the DUT channels by way of the PE channels. Tester software may process the test results to determine whether or not the DUT passed the test.
Often, the tester hardware will include error capture functionality. This functionality may involve storage of error data received on certain PE channels. Memory that stores such error data is herein referred to as the Error Capture RAM (or simply “ECR”). In order to organize the information in the ECR into a useful format for later retrieval, error data from a given PE channel (which corresponds to a corresponding DUT channel or signal pin of the DUT) may be assigned to one or more predetermined bits in the ECR. However, because the tester is designed to test integrated circuit devices of varying designs, the tester must be configured at test setup time to instruct the tester which bits in the ECR correspond to which PE channels (and therefore, ultimately, which DUT channels). That is, data output from the PE channels is routed to various corresponding bits in the ECR according to user specification as set up during configuration of a given test. Typically, PE-channel-to-ECR-channel configuration is performed by specifying an association of each pin of the DUT to a corresponding ECR bit or bits (hereinafter “ECR channel”).
As semiconductor devices become more complicated, the number of DUT channels that require probing is increasing, which increases the complexity of the PE channel configuration. In order to maximize throughput, today's testers often allow multiple DUTs to be tested simultaneously. This is achieved by designating different groups of pin electronics channels to service different DUTs mounted in the tester. While this parallel test execution approach certainly improves over serial testing techniques, the tester configuration required during tester configuration and test setup remains lengthy. This is due to the traditional hardware-centric paradigm of configuring the tester which does not utilize any identification of particular DUTs in its associations between PE channels, tester resources, ECR bits, etc.
For example, referring back to the discussion of the ECR, in the traditional hardware-centric paradigm, PE-channel-to-ECR-channel configuration must still be performed by specifying an association of each pin of each DUT to a corresponding ECR channel, regardless of whether or not the DUTs to be tested are identical. In the typical manufacturing line case in which all of the multiple DUTs to be tested are identical, the advantages afforded by similarity of the DUT designs cannot be exploited if the tester configuration utilizes the DUT-centric approach.
It would therefore be useful to have a tester configuration approach that would allow PE-channel-to-ECR-channel configuration for all DUTs simultaneously, thereby reducing tester configuration time.